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rf signal processor s5l1462b 1 introduction the s5l1462b01 is used for cd and dvd playback. it receives optical signal from the optical pick-up to produce the data-generating rf signal, the servo error signal for stable servo control, and the monitor signal. this rf ic can be used in the cd 1x, 2x, or the dvd 1x clv (constant linear velocity) mode. the dvd mode is compatible with the single/dual layer disc. the cd mode is compatible with the cd-rom, cd-r and cd-rw disc. features can be used with cd 1x, 2x, and dvd 1x playback mode. able to input and handle all optical signal of the cd-r's p/u. built-in pre-amp with adjustable gain, compatible with various p/u. built-in agc (automatic gain control) circuit operated by light detection feedback. built-in rf amp & equalizer compatible with cd 1x, 2x, and dvd 1x. built-in astigmatism method fe (focus error) amp for cd and dvd use. built-in 3-beam te (tracking error) amp for cd. built-in 1-beam dpd (differential phase detector) te amp for dvd. built-in rf mirror detection circuit for cd and dvd. built-in rf defect detection circuit for cd and dvd. built-in fok (focus o.k.) signal detection circuit for cd and dvd. built-in rf envelope signal generating circuit for cd and dvd. built-in interrupt defect detection circuit. built-in alpc (automatic laser power control) circuit for cd and dvd. built-in standard voltage generating circuit for analog circuit use (2.5v, 1.65v). built-in defective waveform detection circuit. power operating range: 4.5 ? 5.5 v, 3.0 ? 3.6 v. 80 pin, qfp. ordering information device package temperature range S5L1462B01-Q0R0 80-qfp-1420c -25 to +70 c 80-qfp-1420c
s5l1462b rf signal processor 2 block diagram 1 2 3 4 rf mux 6 7 8 vref 9 eq vc amp 10 11 12 13 14 15 analog vc amp 16 17 18 19 20 21 22 23 24 alpc alpc_sel 80 79 78 77 76 to rf eq tuning block agc_det pd_pol 75 74 73 72 71 70 69 68 67 66 65 rfsum $ agc amp mux6 rf equalizer agci rfrp eq_freq. eq_boost rfsum_sel 64 63 rfct & mirr 62 61 60 59 58 57 56 55 s/if block 54 53 dpd vc amp 52 51 50 to dpd block 49 48 47 46 45 44 43 interruption detect 42 41 gain_te1 gain_rfum agc_hold agc_lvl gca gca com com dpdeq1 vcps defective waveform detection circuit phase detector lps pllctl tbal pd_limit dpdmute te10fst pdlimitres fault out pllctl flt_ctl hold_ctl gca + - + - gca gain_abcd abcdofst gain_fe feofst a+c b+d + - gain_te3 tfofst lpf 10db inter detect inter_onb te mux te38 lpf 10db 29 28 analog vc1 amp 27 26 25 te_ sel 30 31 32 33 envelope fok 35 34 defect dfctth1 dfctth2 36 37 38 39 40 dpdeq2 gain_fe feofst rfsum advd bdvd ddvd rrefbf rrefeq rref vrefeq advd1 bdvd1 cdvd1 ddvd1 avcc vrefa e f vbgro ld0dvd pddvd ld0cd pdcd agnd fe avcc1 te interb abcd vrefa1 abcdi envp envb env fokb gnd dfct_cp1 dfct_cp2 cc1 cc2 dvcc cp1 cb1 rfrp cp2 cpeak rfct reset stb clock data pdlimiters vrefdpd dpdgnd te1res pllctl faultout dpdeq2 dpdeq1 mirr dpdvcc inter0 inter1 plldft dfct1 pllgf vz0ctl rdpf agcp agcb agcbo eognd agcc rfagco eqin rfeqo agc1in agc1c agc10 eqvcc mirri + - vrefa1 vrefa vrefa vrefaof mux int_onb fok_th sw_con sw_con1 cpeak eq eq te1 front mux inter_th
rf signal processor s5l1462b 3 pin description no. name i/o description related blocks related parts 1 rfsum i rf optical's main beam rfsum ac coupling input pin pre amp p/u 2 advd i rf optical's main beam a ac coupling input pin pre amp p/u 3 bdvd i rf optical's main beam b ac coupling input pin pre amp p/u 4 cdvd i rf optical's main beam c ac coupling input pin pre amp p/u 5 ddvd i rf optical's main beam d ac coupling input pin pre amp p/u 6 rrefbf - rf amp i/o buffer bias resistance connection pin rf amp - 7 rrefeq - rf eq bias resistance connection pin rf eq - 8 rref - analog block bias resistance connection pin analog - 9 vrefeq o rf eq center voltage cap connection pin eq vc amp - 10 advd1 i servo optical's main beam a input pin servo amp p/u 11 bdvd1 i servo optical's main beam b input pin servo amp p/u 12 cdvd1 i servo optical's main beam c input pin servo amp p/u 13 ddvd1 i servo optical's main beam d input pin servo amp p/u 14 avcc p analog part power voltage (5 v) input pin analog - 15 vrefa -/o analog part center voltage cap connection pin. uses another block. ana vc amp servo 16 e i servo cd optical's sub beam e input pin te 3b p/u 17 f i servo cd optical's sub beam f input pin te 3b p/u 18 vbgro i/o alpc bandgap voltage input and bandgap output pin alpc - 19 ldodvd o dvd optical's laser diode operating voltage output pin alpc p/u 20 pddvd i dvd optical's laser monitor diode voltage input pin alpc p/u 21 ldocd o cd optical laser diode operating voltage output pin alpc p/u 22 pdcd i cd optical laser monitor diode voltage input pin alpc p/u 23 agnd p analog part power gnd pin analog - 24 fe o fe amp output pin fe amp dssp 25 interb o interruption button detection time constant cap. connection interruption servo 26 te o te amp output pin te amp dssp 27 avcc1 p analog part power voltage (3.3 v) input pin analog - 28 vrefa1 -/o analog part center voltage1 (1.65 v) cap connection pin ana vc1 amp - 29 abcd o abcd amp output pin abcd amp - 30 abcdi i servo monitor abcd ac coupling input pin servo monit -
s5l1462b rf signal processor 4 pin description (continued) no. name i/o description related blocks related parts 31 envp - rf envelope detecting peak hold time constant selection rc connection pin rf env - 32 envb - rf envelope detecting bottom hold time constant selection rc connection pin rf env - 33 env o rf envelope detect output pin rf env dssp 34 dgnd p digital circuit power gnd input pin digital - 35 fokb o focus ok comparator output pin (l: focus ok) fokb dssp 36 dfct_cp1 - servo defect maximum time selection peak hold time constant connection pin dfct - 37 dfct_cp2 - pll defect minimum time selection peak hold time constant connection pin dfct - 38 cc1 o defect peak detector circuit output pin dfct - 39 cc2 i defect ac coupling input pin dfct - 40 dvcc p digital circuit power voltage (5 v) input pin digital - 41 dfct1 o servo defect output pin defect dssp 42 plldft o pll defect output pin defect pll 43 intero o interrupt defect detection output pin interrupt - 44 interi i interrupt defect detection input pin interrupt - 45 dpdvcc p dpd te power voltage (5v) input pin dpd - 46 mirr o mirror output pin mirr dssp 47 dpdeq1 o dpd eq (a+c) output pin dpd - 48 dpdeq2 o dpd eq (b+d) output pin dpd - 49 faultout o dpd abnormal waveform output pin (monitor) dpd - 50 pllctl i dpd te pll variable input pin dpd servo 51 te1res i dpd te pll variable bias resistance dpd - 52 dpdgnd p dpd te power gnd input pin dpd - 53 vrefdpd o dpd te center voltage cap connection pin dpd vc amp - 54 pdlimitres - pdlimitk bias resistance connection pin dpd - 55 data i data input pin serial interface micom 56 clock i clock input pin serial interface micom 57 stb i data enable input pin serial interface micom 58 reset i serial register reset pin serial interface micom 59 rfct o mirror rf ripple center voltage output pin mirror dssp 60 cpeak - agc/agc1 peaking protection sw control voltage input pin agc/agc1 -
rf signal processor s5l1462b 5 pin description (continued) no. name i/o description related blocks related parts 61 cp2 - rfct generating peak hold time constant rc connection pin mirror - 62 rfrp o mirror rf ripple amp output pin mirror dssp 63 cb1 - rfrp generating bottom hold time constant rc connection pin mirror - 64 cp1 - rfrp generating peak hold time constant rc connection pin mirror - 65 mirri i mirr signal generating input pin mirror - 66 eqvcc p rf eq power voltage input pin rf eq - 67 agc1o o rf agc1 amp output pin rf agc1 - 68 agc1c - agc1 time constant cap connection pin rf agc1 - 69 agc1in i rf agc1 amp input pin rf agc1 - 70 rfeq0 o rf eq output pin rf eq pll 71 eqin i rf eq rfagco input pin rfeq rfenv dssp 72 rfagco o rf agc amp output pin rf agc - 73 agcc - agc time constant cap connection pin rf agc - 74 eqgnd p rf eq power gnd input pin rf eq - 75 agcbo - rf eq bias resistance connection pin rf eq - 76 agcb - rf agc rf bottom hold time constant rc connection pin rf agc - 77 agcp - rf agc rf peak hold time constant rc connection pin rf agc - 78 rdpf - rf eq frequency selection bias resistance connection pin rf eq - 79 vzoctl i rf eq zero control voltage rf eq dssp 80 pllgf i wide range pll rf eq boost, peak frequency gain control pin (internally designed pllg, pllf resistance) rf eq dssp
s5l1462b rf signal processor 6 absolute maximum ratings ( t a = 25 c) item symbol standard value unit notes power voltage vs 6 v operating temperature temp -25 to +70 c power expenditure p d 1100 mw storage temperature tstg -40 to +125 c item symbol standard value unit notes min typ max power voltage vo 4.75 5 5.25 v operating current ic - 120 160 ma
rf signal processor s5l1462b 7 electrical characteristics (v cc = 5v, v cc1 = 3.3v, gnd = 0v, vc = 2.5v, vc1 = 1.65v ta = 25 c, vc is center of standard output voltage.) no item symbol input measuring output unit point min. typ. max. circuit current 1 supply current iccl vdd=4.5v,te1 block operation 80 100 120 ma 2 supply current icct vdd=5v,te1 block operation 100 120 140 ma 3 supply current icch vdd=5.5v,te1 block operation 120 140 160 ma rf sum & agc amp 4 vrfsum1 rfsum=1mhz, 1.5vpp, rfsum_sel=0 gain_rfsum=0db, dvd mode 5 rf sum amp voltage gain vrfsum2 rfsum=1mhz, 1vpp,rfsum_sel=0 gain_rfsum=0db, dvd mode 6 vrfsum3 rfsum=1mhz, 0.1vpp, rfsum_sel=0 gain_rfsum=20db, cd mode rfagco (agc_lvl=0 1h,) 0.8 1 1.2 vpp 7 vrfsum4 (a-d)dvd=1mhz, 0.25vpp, rfsum_sel=1 gain_rfsum=0db, dvd mode 8 rf sum amp unit gain bandwidth frfsum1 rfsum=freq. sweep, 1.0vpp, rfsum_sel=0, gain_rfsum=0db,dvd mode 10 - - mhz 9 frfsum2 rfsum=freq. sweep, 0.1vpp, rfsum_sel=0, gain_rfsum=20db,cd mode 5 - - 10 agc voltage gain gagc1 rfsum=1mhz, 2vpp, rfsum_sel=0 gain_rfsum=0db, dvd mode 0.8 1.0 1.2 vpp 11 gagc2 rfsum=1mhz, 0.5vpp, rfsum_sel=0 gain_rfsum=0db, dvd mode 12 agc amp out. level adjust range vagc1 rfsum=1mhz, 1vpp, rfsum_sel=0 gain_rfsum=0db, agc_lvl=00h, dvd mode 0.3 0.5 0.7 13 vagc2 rfsum=1mhz, 1vpp, rfsum_sel=0 gain_rfsum=0db, agc_lvl=10h, dvd mode rfagco (agchold= l) 0.55 0.75 0.95 vpp 14 vagc3 rfsum=1mhz, 1vpp, rfsum_sel=0 gain_rfsum=0db, agc_lvl=11h, dvd mode 1.00 1.25 1.50
s5l1462b rf signal processor 8 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. agc1 15 agc1 out. level vagc1 agc1in:sin 0.5vpp 5mhz dc 2.5v agc1_hold: 1, agc1_lvl:01, agc1_on:0 agc10 0.8 1 1.2 vpp 16 agc1 out. level 1 vagc11 agc1in:sin 0.5vpp 5mhz dc 2.5v agc1_hold:1, agc1_lvl:00, agc1_on:0 agc10 0.6 0.75 0.9 vpp 17 agc1 out. level 2 vagc12 agc1in:sin 0.5vpp 5mhz dc 2.5v agc1_hold: 1, agc1_lvl:11, agc1_on:0 agc10 1.15 1.45 1.75 vpp 18 band width (-3db) fagc12 agc1in:sin 0.5vpp 5mhz dc 2.5v agc1_hold: 1, agc1_lvl:01, agc1_on:0 agc10 6 - - mhz 19 agc1 normal gain aagc1 agc1in:sin 0.5vpp 5mhz dc 2.5v agc1_hold: 1, agc1_lvl:11, agc1_on:0 agc10 20 db 20 agc1 out. dc vdcagc1 agc1in: dc 2.5v agc1_hold: 1, agc1_lvl:11, agc1_on:0 agc10 2.5 v abcd sum amp 21 abcd sum amp voltage gain vsum1 (a-d)dvd1=0.5mhz, 250mvpp+vc, dvd mode gain_abcd:6db abcd 1.8 2.0 2.2 vpp 22 vsum2 (a-d)dvd1=200khz, 20mvpp+vc, cd mode gain_abcd:30db 23 rf sum amp -3db gain bandwidth fsum1 (a-d)dvd1=freq. sweep,250mvpp+vc, dvd mode, gain_abcd:6db abcd 500 - - khz 24 fsum2 (a-d)dvd1= freq. sweep,125mvpp+vc, cd mode, gain_abcd:12db
rf signal processor s5l1462b 9 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. rf equalizer 25 eq standard output vrfeqdvd eqin=100khz, 1vpp, rfeqo 1.5 2.0 2.3 vpp 26 eq peak frequency fpeakdvd eqin= freq. sweep, 250mvpp eqf=80h eqg=83h 6.4 mhz 27 eq out dc veq_dc eqin=dc 2.5v rfeq0 eqf=80h eqg=83h 2 2.5 3 v 28 f1dvd eqin =0.4mhz, 250mvpp rfeqo eq_boost =0db -2 0 2 29 eq peak frequency dvd f2dvd eqin =3.54mhz, 250mvpp eqg_cen =9db 4.0 6.0 8.0 db 30 f3dvd eqin =6.4mhz, 250mvpp eq_freq =0% 7.0 9.0 11.0 31 f4dvd eqin=12.8mhz,250mvpp -30 -10 0 32 boost gain range dvd gbg1dvd eqin=freq. sweep 250mvpp eqg=80h rfeqo eqf=80h 2 4 6 33 gbg2dvd eqin=freq. sweep 250mvpp eqg=81h 4 6 8 db 34 gbg3dvd eqin=freq. sweep 250mvpp eqg=82h 6 8 10 35 gbg4dvd eqin=freq. sweep 250mvpp eqg=83h 9 11 13 36 f1cd rfsum=0.1mhz, 250mvpp rfeqo eq_boost =0db -1 0 +1 37 eq peak frequency cd f1cd rfsum=0.5mhz, 250mvpp eqg_cen =9db 1.5 3.5 5.5 db 38 f1cd rfsum=0.72mhz, 250mvpp eq_freq =0% 7.0 9.0 11.0 39 f1cd rfsum=1.4mhz, 250mvpp -30 -10 0 40 boost gain range cd gbg1cd eqin=freq sweep 250mvpp eqg=80h 3 4 5 41 gbg2cd eqin=freq sweep 250mvpp eqg=81h rfeqo eqf=80h 4 6 8 db 42 gbg3cd eqin=freq sweep 250mvpp eqg=82h 6 8 10 43 gbg4cd eqin=freq sweep 250mvpp eqg=83h 9 11 13
s5l1462b rf signal processor 10 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. focus error amp 44 vfedvd1 (a,c)dvd1=1khz sine, 630mvpp+vc (b,d)dvd1=1khz sine(i) 630mvpp+vc gain_fe=-2db, dvd mode 45 voltage gain vfedvd2 (a,c)dvd1=1khz sine 63mvpp+vc (b,d)dvd1=1khz sine(i) 63mvpp+vc gain_fe=18db, dvd mode fe 1.8 2.0 2.2 vpp 46 vfecd1 (a,c)dvd1=1khz sine 200mvpp+vc (b,d)dvd1=1khz sine(i) 200mvpp+vc gain_fe=8db, cd mode 47 vfecd2 (a,c)dvd1=1khz sine 40mvpp+vc (b,d)dvd1=1khz sine(i) 40mvpp+vc gain_fe=22db, cd mode 48 output voltage h vfehdvd (b,d)dvd1=vc+0.7v, (a,c)dvd1=vc, gain_fe=-2db, dvd fe 2.8 2.9 v 49 output voltage l vfeldvd (b,d)dvd1=vc-0.7v, (a,c)dvd1=vc, gain_fe=-2db, dvd 0.4 0.5 50 output voltage h vfehcd (b,d)dvd1=vc+0.7v, (a,c)dvd1=vc, gain_fe=0db, cd fe 2.8 2.9 v 51 output voltage l vfelcd (b,d)dvd1=vc-0.7v, (a,c)dvd1=vc, gain_fe=0db, cd 0.4 0.5 52 bandwidth ( -3db freq.) ffedvd (a,c)dvd1=sine 63mvpp+vc (b,d)dvd1=sine(i) 63mvpp+vc gain_fe=18db, freq. sweep, dvd mode fe 25k 35k 45k hz 53 ffecd (a,c)dvd1=sine 63mvpp+vc (b,d)dvd1=sine(i) 63mvpp+vc gain_fe=18db,freq. sweep , cd mode 25k 35k 45k hz 54 offset voltage vosfe (a-d)dvd1=vc, gain_fe=18db,feofst=80h fe -300 0 300 mv
rf signal processor s5l1462b 11 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. tracking error amp (1-beam) 55 dpd eq standard gain vdpdeq1 (a-d)dvd= 500mvpp 200khz sine+vc, gain_te1 = 0db 1.8 2.0 2.2 vpp 56 vdpdeq2 (a-d)dvd= 45mvpp 200khz sine+vc, gain_te1 = 27db dpdeq1 dpdeq2 57 dpd eq gain characteristics variable range gdpdeqr (a-d)dvd: 251mvpp freq. sweep sine+vc, gain_te1 = 12db (int_onb=1 flt_cnt=1) 4 8 11 db 58 vph0 (a-d)dvd: 251mvpp 5mhz sine+vc (a,c)dvd, (b,d) dvd's phase difference 0 gain_te1 = 12db 1.2 1.65 2.1 v 59 output voltage correspond to phase difference vph1 (a-d)dvd: 251mvpp 5mhz sine+vc when (a,c) dvd's phase difference is 45 ahead of (b,d)dvd, gain_te1 = 12db te (int_onb=1 flt_cnt=1) 0.05 0.65 1.05 v 60 vph2 (a-d)dvd: 251mvpp 5mhz sine+vc when (a,c) dvd's phase difference is 45 behind (b,d)dvd gain_te1 = 12db 2.25 2.65 3.25 v 61 tracking balance adjustment range vbal1 (a,c)dvd=251mvpp 2.616mhz sine + vc (b,d)dvd=251mvpp 2.616mhz sine + vc tbal=00h, gain_te1=12db te (int_onb=1 flt_cnt=1) 0.33 v 62 vbal2 (a,c) dvd=251mvpp 2.616mhz sine + vc (b,d) dvd=251mvpp 2.616mhz sine + vc tbal=ffh, gain te1=12db 2.97 63 phase comparator limit vphlim1 (a,c)dvd=2mhz, 300mvpp, duty 50% pulse (b,d)dvd signal with a phase 90 late pd_limit=90ns te (int_onb=1 flt_cnt=1) 2.55 3.25 v 64 vphlim2 (b,d)dvd=2mhz, 300mvpp, duty 50% pulse (a,c)dvd signal with a phase 90 late pd_limit=90ns 0.05 0.75 65 abnormal waveform detection circuit tflt (a,c)dvd=251mvpp,100khz (b,d)dvd=251mvpp,2.616mhz time measurement from falling edge with only (b,d)dvd, to when faulto becomes h (b,d)dvd faulto 450 900 ns 66 offset voltage voste1 (a,.b)dvd. (b.d) dvd =vc gain_te1=27db teofst=80h te (int_onb=1 flt_cnt=1) -300 0 300 mv
s5l1462b rf signal processor 12 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. tracking error amp (3-bearn) 67 te3 voltage gain vte31 e=1khz sine 316mvpp+vc f=1khz sine(i) 316mvpp+vc tbal=80, gain_te3=10db, teofst=80h te 1.8 2.0 2.2 vpp 68 vte32 e=1khz sine 30mvpp+vc, f=1khz sine(i) 30mvpp+vc, tbal=80, gain_te3=30db, teofst=80h te 69 out. voltage h vte3h e=vc-0.7v,f= vc,gain_fe=10db te 2.8 2.9 v 70 out. voltage l vte3l e=vc+0.7v,f=vc,gain_fe=10db te 0.4 0.5 71 bandwidth (-3db freq.) fte3 e=sine 316mvpp+vc, freq. sweep f=sine(i) 316mvpp+vc, freq. sweep tbal=80h, gain_te3=10db, teofst=80h te 45k 60k 75k hz 72 tracking balance range gte31 e=1khz sine 316mvpp+vc f=1khz sine(i) 316mvpp+vc tbal=00h, gain_te3=18db, teofst=80h te 3 - - db 73 gte32 e=1khz sine 316mvpp+vc f=1khz sine(i) 316mvpp+vc tbal=ffh, gain_te3=18db, teofst=80h - - -3 db 74 offset voltage voste3 e,f=vc,tbal=80, gain_te3 =26db, te3ofst=80h te -300 0 300 mv 75 tracking offset range voste31 e,f=vc, tbal=80, gain=te3=26db teofst=00h te 0 0.5 v 76 voste32 e,f=vc, tbal=80, gain=te3=26db teofst=ffh te 0.3 3.3 v
rf signal processor s5l1462b 13 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. mirror circuit 77 output voltage h vmirh mirri=1vpp 1khz sine 30% am fc = 5mhz mirr 4.5 - - v 78 output voltage l vmirl dc=2.5v rfrpofst=30 rfrp_frq=30khz gain_rfrp=14db - - 0.4 79 mirr hold frequency fhold1 (dvd) measure the freq. of no 65 mirr 990 1000 1010 hz 80 fhold2 (cd) mirri=1vpp 1khz sine 30% am fc=5mhz dc=2.5v, rfrpofst=30 rfrp_frq=320khz gain_rfrp=14db 99 100 101 khz 81 rfrp output level 1 vrfrp1 (dvd) mirri=1vpp 1khz sine 30% am fc=5mhz dc=2.5v rfrp_ofst=30 rfrp_frq=30khz gain_rfrp=12db rfrp 1.0 1.15 1.30 vpp 82 vrfrp2 (cd) mirri=1vpp 1khz sine 30% am fc=500khz dc=2.5v rfrp_ofst=30 rfrp_frq=30khz gain_rfrp=12db 83 rfrp output level 2 vrfrp3 (dvd) mirri=1vpp 20khz sine 30% am fc=5mhz dc=2.5v rfrp_ofst=30 rfrp_frq=30khz gain_rfrp=12db rfrp 700 850 1000 mvpp 84 vrfrp4 (cd) mirri=1vpp 300khz sine 30% am fc=5mhz dc=2.5v rfrp_ofst=30 rfrp_frq=320khz gain_rfrp=12db 300 450 600 85 rfrp output variable range avorfrp1 mirri=1vpp 1khz sine 30% am fc=5mhz dc=2.5v rfrp_ofst=30 rfrp_frq=30khz gain_rfrp=12db rfrp 4.5 6 7.5 db 86 avorfrp2 mirri=1vpp 1khz sine 30% am fc=500khz dc=2.5v rfrp_ofst=30 rfrp_frq=320khz gain_rfrp=14db 6.5 8 9.5
s5l1462b rf signal processor 14 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. mirror circuit 87 rfrp bandwidth (-3db) frfrp1 mirri=1vpp 60khz sine 30% am fc=5mhz dc=2.5v rfrp_ofst=30 rfrp_frq=30khz gain_rfrp=12db rfrp 60 khz 88 frfrp2 mirri=1vpp 120khz sine 30% am fc=5mhz dc=2.5v rfrp_ofst=30 rfrp_frq=30khz gain_rfrp=12db 120
rf signal processor s5l1462b 15 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. defect detect circuit 89 output voltage h vdefh (a-d)dvd1=1khz 250mvpp+vc gain_abcd=0db abcdofst=80 4.5 v 90 output voltage l vdefl (a-d)dvd1=1khz 250mvpp+vc gain_abcd=0db abcdofst=80 0.4 91 min operation frequency fdef1 (a-d)dvd1=1khz 250mvpp+vc gain_abcd=0db abcdofst=80 dfct dftp_th 1.0 khz 92 max operation frequency fdef2 (a-d)dvd1=5khz 250mvpp+vc gain_abcd=0db abcdofst=80 =300mv dft_th 5.0 93 minimum input operation voltage vdefin1 (a-d)dvd1=5khz 150mvpp+vc gain_abcd=0db abcdofst=80 =100mv 0.5 vpp 94 maximum input operation voltage vdefin2 (a-d)dvd1=5khz 600mvpp+vc gain_abcd=0db abcdofst=80 1.8 95 high speed peak hold time constant range tphr1 (a-d)dvd1: 250mvpp+vc square 5khz gain_abcd=0db dfct_cnst=5.6us/v 5.7 us/v 96 tphr2 (a-d)dvd1: 250mvpp+vc square 5khz gain_abcd=0db dfct_cnst=60us/v 60 fok detect circuit 97 output voltage h vfokh (a-d)dvd1=250mvpp 1khz sine fokb 4.5 v 98 output voltage l vfokl wave, gain_abcd=0db fok_th=80 0.4 99 maximum operation frequency ffok (a-d)dvd1=250mvpp 45khz gain_abcd=0db, fok_th=80 fokb 45k hz rf envelope amp 100 output voltage venv abcdi : 2vpp,sine 1mhz env 1.66 1.86 2.06 v alpc circuit 101 output voltage h valpch1 pddvd: +600v ldonb=1 (ldo) dvd 4.5 v 102 output voltage l valpcl1 pddvd: +0v ldonb=1 (ldo) dvd 0.5 103 output voltage h valpch2 pdcd: +600mv ldonb=1 (ldo) cd 4.5 v 104 output voltage l valpcl3 pdcd: +0mv ldonb=1 (ldo) cd 0.5 105 input pd voltage vinpd pddvd: dc sweep ldonb=1 pd value when lddvd: 3.5v ldo dvd 158 178 198 mv
s5l1462b rf signal processor 16 electrical characteristics (continued) no item symbol input measuring output unit point min. typ. max. interrupt detect circuit 106 output voltage1 h vinth1 interi=1vpp 1khz inter_th=80 gain_int=3.5db int_sel=1, intero 4.5 v 107 output voltage1 l vintl1 int_onb=0 0.4 108 output voltage2 h vinth2 (a-d)dvd1=1khz, 250mvpp+vc, dvd mode gain_abcd:6db inter_th=80 intero 4.5 v 109 output voltage2 l vintl2 gain_int=3.5db, int_sel=0, int_onb=0 0.4 110 minimum operation frequency 1 fint11 interi=1vpp, 1khz inter_th=80 gain_int=3.5db int_sel=1, int_onb=0 intero 1.0 khz 111 maximum operation frequency 1 fint21 interi=1vpp, 5khz inter_th=80 gain_int=3.5db int_sel=1, int_onb=0 5.0 112 minimum operation frequency 2 fint12 (a-d)dvd1=1khz, 250mvpp+vc, dvd mode inter_th=80, gain_int=3.5db int_sel=0, int_onb=0 intero 1.0 khz 113 maximum operation frequency 2 fint22 (a-d)dvd1=5khz, 250mvpp+vc, dvd mode inter_th=80, gain_int=3.5db int_sel=0, int_onb=0 5.0 114 minimum input operation frequency vintin1 interi=0.5vpp, 5khz pulse symmrtry=90%, inter_th=80 gain_int=9.5db, int_sel=1, int_onb=0 intero 0.5 vpp 115 maximum input operation frequency vintin2 interi=1.8vpp, 5khz pulse symmrtry=90%, inter_th=80 gain_int=3.5db, int_sel=1, int_onb=0 1.8 input2 input1 frequency = fin1*2,duty=50% frequency = fin1,duty=25% 300mvpp 300mvpp
rf signal processor s5l1462b 17 serial interface the serial interface controls the disc type, speed, agc, and the on/off of the laser diode. the serial interface's timing diagram is as follows. address, 8-bit data, 8-bit stb data clock a7 a0 d7 d0 serial port data transfer format ? clock : clock synchronous to the data transmitted from micom. ? data : address and data transmitted from micom. ? stb : signal showing that data is enabled. address : 00h data d7 d6 d5 d4 d3 d2 d1 d0 function agc_hold te_sel rfsum_sel buf_sel ldonb agc_hold speed_sel initial value 0 0 0 0 0 0 0 0 agc1_hold(d7): rf agc peaking protection selection 0: unuse 1: use te_sel(d6): tracking error selection 0: dpd 1: te3 rfsum_sel(d5): rfsum port selection 0: rfsum input 1: (a, b, c, d) input buf_sel(d4): input buffer selection (rfsum port polarity selection) 0: buffer bypass 1: buffer use ldonb(d3): laser,on/off control pin 0:laser off 1:laser on agc1_hold: agc1 peaking protection selection 0: unuse 1: use speed_sel (d1 - d0) : speed selection d1 d0 mode speed_sel 0 0 dvd 1x 1 0 cd 1x 1 1 cd 2x
s5l1462b rf signal processor 18 address 01h : tracking balance adjustment data d7 d6 d5 d4 d3 d2 d1 d0 function tbal initial value 1 0 0 0 0 0 0 0 3 beam te: f's relative change in gain compared to e, following the value change of tbal . tbal f gain 00 +4db 80 0db ff -4db dpd te: the change in the te output voltage following the change in the tbal value. tbal te output voltage 00 -1.2v 80 0v ff +1.2v address 02h : gain_rfsum, gain_te3 gain selection data d7 d6 d5 d4 d3 d2 d1 d0 function gain_rfsum gain_te3 initial value 0 0 0 1 0 0 1 0 gain_rfsum (d4 - d7) : rf sum input pin gain selection d7 d6 d5 d4 mode (value of rfagco compared to the input voltage) 0 0 0 0 -6db 0 0 0 1 -4db 0 0 1 0 -2db 0 0 1 1 0db 0 1 0 0 2db 0 1 0 1 4db 0 1 1 0 - 0 1 1 1 - 1 0 0 0 6db 1 0 0 1 8db 1 0 1 0 10db 1 0 1 1 12db 1 1 0 0 14db 1 1 0 1 16db 1 1 1 0 - 1 1 1 1 -
rf signal processor s5l1462b 19 gain_te3 (d0 - d3) : te3 gain selection d3 d2 d1 d0 gain 0 0 0 0 6db 0 0 0 1 8db 0 0 1 0 10db 0 0 1 1 12db 0 1 0 0 14db 0 1 0 1 16db 0 1 1 0 18db 0 1 1 1 20db 1 0 0 0 - 1 0 0 1 - 1 0 1 0 - 1 0 1 1 - 1 1 0 0 - 1 1 0 1 - 1 1 1 0 - 1 1 1 1 -
s5l1462b rf signal processor 20 address 03h : gain_fe, gain_abcd gain selection data d7 d6 d5 d4 d3 d2 d1 d0 function gain_abcd gain_fe initial value 0 0 1 0 0 0 1 1 gain_abcd (d4 - d7) : abcd gain selection d7 d6 d5 d4 gain 0 0 0 0 0db 0 0 0 1 2db 0 0 1 0 4db 0 0 1 1 6db 0 1 0 0 8db 0 1 0 1 10db 0 1 1 0 12db 0 1 1 1 14db 1 0 0 0 16db 1 0 0 1 18db 1 0 1 0 20db 1 0 1 1 22db 1 1 0 0 24db 1 1 0 1 26db 1 1 1 0 28db 1 1 1 1 30db
rf signal processor s5l1462b 21 gain_fe (d0 - d3) : fe gain selection d3 d2 d1 d0 gain 0 0 0 0 -2db 0 0 0 1 0db 0 0 1 0 2db 0 0 1 1 4db 0 1 0 0 6db 0 1 0 1 8db 0 1 1 0 10db 0 1 1 1 12db 1 0 0 0 14db 1 0 0 1 16db 1 0 1 0 18db 1 0 1 1 20db 1 1 0 0 22db 1 1 0 1 24db 1 1 1 0 26db 1 1 1 1 28db address 04h - 06h : various offset adjustment data address data initial value 04h te(1,3) offset 80h 05h fe offset 80h 06h abcd sum offset 80h the output offset is at its minimum at 00h, maximum at ffh, and 2.5 v at 80h.
s5l1462b rf signal processor 22 address 07h: dpd pd limit gain_te1 hold_ctl selection data d7 d6 d5 d4 d3 d2 d1 d0 function dpd_mute gain_te1 pd_limit initial value 0 0 1 0 0 0 0 0 dpd_mute (d7): dpd te input pin gain selection 0: dpd mute off 1: dpd mute on gain_te1 (d4 - d6): dpd te input pin gain selection d6 d5 d4 mode (relative value of dpdeq1, 2 compared to the voltage) 0 0 0 6db 0 0 1 9db 0 1 0 12db 0 1 1 15db 1 0 0 18db 1 0 1 21db 1 1 0 24db 1 1 1 27db pd limit (d0 - d3): dpd phase detector's limit of output width d3 d2 d1 d0 limit of width 0 0 0 0 160ns ? ? 1 1 1 1 10ns
rf signal processor s5l1462b 23 address 08h: offset adjustment address data initial value 08h rfrp offset 80h the output offset is at its minimum at 00h, maximum at ffh, and 2.5v at 80h. address 0ah: data d7 d6 d5 d4 d3 d2 d1 d0 function eq _freq initial value 1 0 0 0 0 0 0 0 eq_freq (d0 - d7): eq frequency characteristic's minute adjustment selection eq_freq amount of peak frequency change 22 +60% ? ? 80 0% ? ? db -60%
s5l1462b rf signal processor 24 address 0bh : data d7 d6 d5 d4 d3 d2 d1 d0 function eq_boost ga-mux-te eqg_cen initial value 1 0 0 0 0 0 1 0 eq_boost(d4 ? d7) : gain minute adjustment selection from the eq_boost gain chosen by eqg_cen d7 d6 d5 d4 center gain change in width 0 0 1 0 -4db - - 0 1 1 1 -0.5db 1 0 0 0 0db 1 0 0 1 +0.5db - - 1 1 0 0 4db ga-mux-te(d2 - d3) : te output gain control d3 d2 center_boost gain 0 0 10db 0 1 12db 1 0 14db 1 1 16db eqg_cen(d0 - d1) : eq_boost gain's center gain minute adjustment selection d1 d0 center_boost gain 0 0 3db 0 1 5db 1 0 7db 1 1 9db address 0ch : data d7 d6 d5 d4 d3 d2 d1 d0 function rfrp_frq gain_rfrp rfrp-lpf sw-con sw_con1 initial value 0 0 0 0 0 0 0 0 rfrp_frq (d6 - d7) : rfrp's peak-bottom hold circuit output frequency, lpf frequency selection d7 d6 rfrp freq. rfrp lpf fc 0 0 30 khz 60 khz 0 1 80 khz 160 khz 1 0 160 khz 320 khz 1 1 320 khz 640 khz
rf signal processor s5l1462b 25 gain_rfrp (d4 - d5) : rfrp's output gain selection d5 d4 gain_rfrp 0 0 6db 0 1 9.5db 1 0 12db 1 1 14db rfrp_lpf (d3 - d2): rfrp's output gain selection d3 d2 rfrp_lpf 0 0 60khz 0 1 80khz 1 0 100khz 1 1 120khz sw_con (d1): defect signal selection when rf agc/agc1 peaking protection selection 0: un use 1: use sw_con1 (d0): cpeak signal selection when rf agc/agc1 peaking protection selection 0: unuse 1: use address 0dh data d7 d6 d5 d4 d3 d2 d1 d0 function agc_lvl dftp_th dft_th initial value 0 1 0 0 0 0 0 0 agc_lvl(d6 - d7) : rfagc level selection d7 d6 agc level output vpp 0 0 3.25v 0.50vpp 0 1 3.5v 0.75vpp 1 0 3.75v 1.00vpp 1 1 4.0v 1.25vpp dftp_th(d3 - d5) : pll defect slice level selection d5 d4 d3 slice level 0 0 0 300mv 0 0 1 400mv 0 1 0 500mv 0 1 1 600mv 1 0 0 700mv 1 0 1 800mv 1 1 0 900mv
s5l1462b rf signal processor 26 1 1 1 1000mv
rf signal processor s5l1462b 27 dft_th(d0 - d2) : defect slice level selection d2 d1 d0 slice level 0 0 0 100mv 0 0 1 200mv 0 1 0 300mv 0 1 1 400mv 1 0 0 500mv 1 0 1 600mv 1 1 0 700mv 1 1 1 800mv address 0eh: interrupt threshold level selection data d7 d6 d5 d4 d3 d2 d1 d0 function inter_th initial value 1 0 0 0 0 0 0 0 interrupt level selection by the 8-bit dac address 0fh :fok threshold level selection data d7 d6 d5 d4 d3 d2 d1 d0 function fok_th initial value 1 0 0 0 0 0 0 0 fokb level selection by the 8-bit dac
s5l1462b rf signal processor 28 address 10h data d7 d6 d5 d4 d3 d2 d1 d0 function int_onb flt_ctl dfct_cnst ld_sel int_sel agc1_lvl initial value 0 0 0 0 0 0 0 0 agc1_lvl(d0 - d1) : agc1 output level adjustment selection d1 d0 agc1_lvl output level 0 0 2.9v 0.7v 0 1 3.0v 1.0v 1 0 3.1v 1.4v 1 1 - - int_sel (d2): interruption input selection 0: internal input 1: external input ld_sel(d3) : ld output selection 0 : select lddvd 1 : select ldcd dfct_cnst(d4 - d5) : peak hold time constant selection for deciding the defect circuit's defect minimum detection width d5 d4 defect 0 0 60us/v 0 1 25us/v 1 0 12.5us/v 1 1 5.6us/v flt_ctl(d6) : fault out output selection. 0: fault out output on 1: fault out output off int_onb(d7) : interruption on/off selection. 0 : interrupt detect on 1 : interrupt detect off
rf signal processor s5l1462b 29 address 11h data d7 d6 d5 d4 d3 d2 d1 d0 function rvsn vdc25_sel vbgo_ sel dvctl_ sel vdc125_ sel agc1_on gain_int initial value 0 0 0 0 0 0 0 0 gain_int(d0 - d1) : interruption gain adjustment selection d1 d0 gain drainage 0 0 3.5db x1.5 0 1 6db x2 1 0 9.5db x3 1 1 12db x4 agc1_on (d2) : agc1 block on/off adjustment selection 0 : agc1 on 1 : agc1 off vdc125_sel (d3): 1.25v reference voltage selection 0: bandgap voltage use 1: reference voltage use dvctl_sel (d4): te1 input selection 0: (a+b), (b+d) 1: (a+d), (c+d) vbgo_sel (d5): alpc reference voltage input selection 0: internal bandgap reference voltage 1: external voltage vdc25_sel (d6): 2.5v reference voltage selection 0: bandgap voltage 1: reference voltage
s5l1462b rf signal processor 30 block description rf multiplexer rfsum_sel buf_sel cdvd ddvd bdvd rf mux rfsum vrefo rfp1 rfp2 rfp3 rfp4 advd the rf multiplexer is a block that inputs into the rf sum amp the i/v signals which are output differently according to each pickup, in order to get the rf aum signal. the rfsum generates rf signals by compensating according to the i/v polarity using the address 00h's buf_sel. the rf mux's operation is selected by address 00h's rfsum_sel register, and the rf mux output value for each rfsum_sel are as follows. ? rfsum_sel (d3): inputs and selects rfsuum amp's operation mode by address 00h's (d5). (abcd mux & rfsum) d3 rfp1 rfp2 rfp3 rfp4 0 rfsum vrefo vrefo vrefo 1 advd bdvd cdvd ddvd
rf signal processor s5l1462b 31 rf sum & agc amp block gain_rfsum rfagco rfp1 rfp2 rfp3 rfp4 eqin vcc gnd agcb agcp agc_lvl gnd agcc rf sum agc amp + + + + bottom + - peak comp + - + - sw control on/off the rf sum amp either adds or subtracts the input signal selected in the rf multiplexer by the rfsum_sel and compensates according to the i/v polarity using address 00h's buf_sel, to produce the rf signal. also, the rf sum amp is able to adjust the level by the gain selected by gain_rfsum (-6 ? -16db). the rf agc circuit makes the signal whose gain was adjusted by the rfsum amp into a regular size. the agc circuit ' s output size is selected according to the value of agc_lvl (3.2v ? 3.75v), between 0.5vpp -- 1.25vpp in increments of 0.25vpp step. the agc ' s response time constant is decided by the resistance capacity of the capacitor connected to the external connection pin (agcp, agcb, agcc). sw is prohibited the peaking by hold the agc voltage when meet the defect or interruption
s5l1462b rf signal processor 32 rf equalizer rf equalizer rfeqo pllgf eq_freq eq_boost eqg_cen eqin from d.r eqctl rfeq_sel h(s)=k(s 2 -a 2 ) symmetric zero hpf order 9 bessel lpf the rf equalizer receives the rf agc amp's output signal and corrects the gain and frequency characteristics according to disc type and speed. our rf is used in common with the rf eq that has similar frequency characteristics. the rf eq has 3 independent eq characteristics, namely that of dvd 1x, cd 1x, and cd 2x. the rf equalizer is composed of the symmetric zero hpf and the 9th degree bessel lpf. the symmetric zero hpf's transmission function is: h(s) = k(s 2 -a 2 ), and is combined with bessel lpf to make rf eq characteristics. the rf eq has predetermined frequency characteristics according to disc type and speed mode. the minute adjustments of frequency and boost gain are carried out by add 0ch's eq_freq and add 0bh's eq_boost and eqg_cen. the gain adjustment of the peaking frequency is carried out by the combination of gain (3-9db, 2db/step) selected by eqg_cen, and gain (-4.0-+4.0db, 0.5db/step) selected by eq_boost. the selection of the peaking frequency is made by the eq_freq. of the rf eq characteristics from speed_sel selection, the characteristics when eq_freq=0%, eqg_cen=5db, and eq_boost=+1db have been shown below.
rf signal processor s5l1462b 33 frequency gain eq range f peak gpeak characteristics of rf eq eq_freq=0%, eqg_cen=7db, eq_boost=0db spped_sel rf eq fpeak gpeak 00 rf eq1 6.4mhz +7db 10 rf eq2 1.3mhz +7db 11 rf eq3 2.6mhz +7db the rf eq's peak frequency is the same as shown in the above rf eq characteristics. it is therefore able to adjust to the optimal eq characteristics demanded by the system by eq_freq's minute tuning.
s5l1462b rf signal processor 34 dpd tracking error amp ddvd cdvd advd bdvd pllctl dpdte to mux5 + tbal dpd_mute te1ofst gca flt_ctl hold_ctl gain_te1 speed_sel faulto pdmimitres dpdeq2 dpdeq1 dpd te block te1res gnd pd_limit intero eq comp + + gca + eq comp vcps abnormal waveform detection circuit phase detecter lpf te1 front mux the (a-d)dvd signal's gain is adjusted in the dpd input gain adjustment block by the gain selected by address 07h's gain_te1 register. the signal is then compensated in the dpd equalizer and input into the comparator. the signal by passing through the comparator circuit is then adjusted for tracking balance by the vcps (voltage controlled phase shift) circuit, whose delay time is adjusted by address 01h's register tbal. the signal, after passing through the vcps circuit, detects the phase difference between two signals through the phase detector. the maximum width of the phase detector's output is limited by the output width limit set by add 07h's pd_limit register. the abnormal waveform detection circuit compensates for a small or unstable input signal. it executes mute when an abnormal waveform is detected, and turns the detection/compensation on or off. the following are qualified as abnormal waveforms: ? when the a+c comparator output is maintained for longer than 16t. ? when the - b+d comparator output is maintained for longer than 16t ? when the output of the abnormal waveform detection circuit goes "h". ? when the output of the abnormal waveform detection circuit goes 'h', then goes back to "l" at the next rising or falling edge. the output of the phase detector is output through the low pass filter. it is input into the mux5 then output to the te block. the dpd te offset is a function to correct the circuit offset after phase comparison. it eliminates any offset existing within the lpf block. the dpd mute mutes the dpd te while correcting the dpd offset. mute is carried out when add 07h's dpd_mute register is "h", the external dpdmute block's input voltage is "h", and the interrupt output is "h". when te_sel is not in dpd mode, the dpd block's power is turned off.
rf signal processor s5l1462b 35 3b te amp and te output selection te3b tbal te_sel gain_te3 teofst tedpd e f te + - gca m u x 10db - 16db lpf ga_mux_te tracking balance is carried out in the following manner. the gain of the f signaling amp is adjusted by the t_bal (tracking balance) so that the ac level of the e, f signal input becomes the same. after the balance has been adjusted, the e,f signal is operated on in the 3-beam tracking error amp by te = k (e-f). then the gain is compensated by address 02h's gain_te3 from 6db - 20db to compensate for the difference in disc reflectivity according to disc type. the offset is compensated by te0fst, and the signal is output as a te3b signal. the te3b signal is output when the te_sel selects either the dpd te or the 3b te output. the mux te output signal is output through the lpf (fc=20.4khz) and the 10db amp. the servo control voltage output is compatible with the 3.3v supply. focus error amp - + fe a c b d gain_fe feofst inv amp vc lpf inv amp the (a+c), (b+d) input signal is operated on in the focus error amp by fe = -k((a+c)-(b+d)). the gain is compensated by address 03h's fe_gain from -2db - +28db to account for the difference in disc reflectivity according to disc type. when the offset is adjusted by feofst, the signal is output as an fe signal after passing through the lpf (fc=34.7khz) and the inversion amp. the output is a servo control voltage and is compatible with the 3.3v supply.
s5l1462b rf signal processor 36 abcd sum amp - + a c b d inv amp 15db gain_abcd abcd abcd_ofst the input signals a, b, c, d are operated as abcd = a+b+c+d in the abcd sum amp. the gain is compensated by address 03h's gain _abcd from 0db - +30db to account for the difference in disc reflectivity according to disc type. the offset is adjusted by the bacdofst, then the signal is output as abcd. the frequency characteristics of the output amp are fc = 4mhz when in cd 2x mode, and fc=10mhz in dvd mode. fok detect circuit - + abcd fokb fok_th abcdi comp - + this circuit generates the focus ok signal for the servo. it consists of a circuit that detects the peak of the abcd sum signal, and the circuit that outputs the fokb signal. it compares and outputs the abcd sum signal's output signal and the comparison level(fok_th).
rf signal processor s5l1462b 37 mirror circuit gain_rfrp rfrp_ofst mirri vcc rfrp_frq cb1 cp1 cp2 rfct mirr rfrp - + gca peak bottom gnd lpf peak - + comp gnd the rfrp circuit is a block that detects signals crossing the track. the circuit receives ac-coupled rfagco signals and calculates the difference between two signals through the peak hold and bottom hold. the response time constant of the peak hold and bottom hold is set by add 0ch's rfrp_frq, and the standard capacitor value is set by the cp1 block and capacitor connected to the cb1 block. (standard value: 100pf) the amp that produces the rfrp signal by calculating the peak hold output and the bottom hold output receives the rfrp_ofst, and corrects the difference in dc value in the peak hold output and bottom hold output to guarantee a dynamic range and adjust the gain by gain_rfrp from 0db-12db. the rfrp signal is output through the r, c 1st lpf, and the lpf's bw is decided by address 0ch's rfrp_frq value. the center voltage of the two signals that passed through the peak hold and bottom hold is output to the rfct block. the response time constant of the peak hold and bottom hold is decided by the capacitor value and resistance connected to cp2 and cb2. the mirr signal is found by comparing the rfct and rfrp signal, and the polarity is high in the mirror while low in the pit. also, the amount of hysterisis can be adjusted by inserting resistance between the rfct and mirr.
s5l1462b rf signal processor 38 rf envelope circuit vcc peak bottom env envb envp abcdi gnd - + 3.5db level shift this circuit detects the rf envelope rf signal's envelope. it has the envelope detection output for adjusting the servo's focus bias. the peak hold and bottom hold's response time constant is decided by the capacitor value connected to the external block envp, envb, and the standard response frequency is 10 khz (when c = 0.01uf). the level shift circuit is to make sure envout starts near 0volts instead of at vc level when there is no rf signal. during focus un-locking, the circuit outputs to the env output block after 3.5db gain up. the env signal is output to the env output block during focus un-locking after 3.5db gain up.
rf signal processor s5l1462b 39 defect detect circuit peak dfct abcd gnd dfct_cp2 gnd dfct_cp1 cc1 cc2 dftp _th dfct1 dft _th dfct2 rfrp_frq plldft intero gnd peak long - + comp - + comp the defect circuit detects the signal defects from damage to the reflective surface. the defects are detected in abcd through high speed peak hold and low speed peak hold. dc is added to the high speed peak hold output, then compared with the low speed peak hold output. the high speed peak hold's response time constant is set to add 0ch's rfrp _frq when a defect is detected. the low speed peak hold time constant is set by the capacitor connected to the rfrp_frq and cb_dft block. the rate of change is same for high and low speed peak hold. the defect detecting level for servo is set by add 0dh's dft_th, and the defect detecting level for pll is set by dftp_th. the output of the servo's defect is oring with the interrupt output. interrupt defect circuit gnd vrefa interi intero int_onb inter_ th vrefa gain_int - + - + comp the interrupt defect circuit detects signal defects from insulation layer damage during cd/dvd mode operation. the abcdsum output passes through the external lpf, is amplified by the amp, then comparatively output with the comparator's standard voltage (inter_th). the amp's gain is adjusted by the gain_int, and this interrupt signal's use is determined by int_onb.
s5l1462b rf signal processor 40 alpc circuit ld_sel pddvd vcc 20k gnd ldodvd pick-up vcc gnd ld_sel pdcd vcc gnd ldocd pick-up vcc - + 3.5k mux + + 3.5k 20k mux + gnd + - + - + vbgo this circuit is for controlling the laser diode's amount of light. it sets the amount of light that is output during playback, and stabilizes it by detecting the fluctuation in laser power for voltage or temperature change using the monitor photo diode's output current change. alpc for cd and dvd are separate. alpc circuit selection and on/off are controlled by add 00h's ldonb. the unselected alpc maintains off status. the alpc reacts to the p-sub laser diode. its standard voltage can be changed by the value of the external zener diode connected to the vreflp_bgi block. pd's standard input voltage range is 100mv -- 0.5v.
rf signal processor s5l1462b 41 test circuit dpdvcc dpdgnd eqvcc eqvgnd rfsum advd bdvd cdvd ddvd rrefbf rrefeq rref vrefeq advd1 bdvd1 cdvd1 ddvd1 avcc vrefa e f vreflp_bgi ldodvd pddvd ldocd pdcd agnd fe ce te avcc1 vrefa1 abcd abcdi envp envb env dgnd fokb dfct_cp1 dfct_cp cc1 cc2 dvcc dfct1 plldft interi intero dpdvcc mirr dpdeq1 dpdeq2 faultout pllctl te1res dpdgnd vrefdpd pdlimitres data clock stb reset rfct cb2 cp2 rfrp cb1 cp1 mirri eqvcc rfeqo eqin rfagco agcc eqgnd agcbo agcb agcp rdpf vzoctl pllgf agc1in agc1c agc1o s5l1462b c6_1:102 c6 :103 c7 :473 c8 :473 c9 :224 c10 :100p c11 :224 r4 :100k r5 :100k c12 : 100n (104) c13 : 50n c14 : 50n c15 : 0.1u c16 : 100p c100: 104 c1: 224 c2 - c5: 0.1u r1: 12k r2: 12k r3: 12k c17 : 0.01u c18 : 0.1u c19 : 0.47u c20 : 0.01u c21 : 0.01u c22 : 0.01u r12 : 100k r13 : 100k r14 : 5k r15 : 20k 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 r15 c21 r12 c22 r13 r14 vzoctl pllgf c20 c19 sw5 sw4 c17 agcbo agcc rfagco eqin bnc bnc agc1in rfeqo agc1o agc1c bnc mirri c1 c2 c3 c4 c5 r1 r2 r3 bnc bnc bnc rfsum a b sw1 abcd vrefa bnc bnc e f vfefpl_ bgi ld pd fe c6_1 te vrefa1 abcd abcdi c7 r4 sw2 c8 env bnc dvcc dgnd fokb dfct_cp1 c9 c10 dfct_cp c11 r6 : 12k r7 : 12k r8 : 27k r9 : 33k r10 : 100k r11 : 100k r12 : 1k dfct1 plldft r100 interi c100 bnc intero c12 sw3 mirr dpdeq1 dpdeq2 pllctl faultout r6 vrefdpd r7 data clock stb reset rfct r8 r9 cpeak r11 c14 rfct rfrp c15 c16 electrolytic electrolytic electrolytic cap agnd avcc electrolytic electrolytic electrolytic
s5l1462b rf signal processor 42 package dimension #80 20.00 23.90 + 0.30 14.00 17.90 + 0.30 #1 0.80 0.35 + 0.10 note : dimensions are in millimeters. 0.15 max (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 + 0.20 0.05 min 2.65 + 0.10 3.00 max 0.80 + 0.20 (1.00)
rf signal processor s5l1462b 43 notes

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